author        = {Thomas Plos and Michael Hutter and Martin Feldhofer and Maksimiljan Stiglic and Francesco Cavaliere},
  title         = {Security-Enabled Near-Field Communication Tag With Flexible Architecture Supporting Asymmetric Cryptography},
  journal       = {IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
  volume        = {21},
  number        = {11},
  year          = {2013},
  pages         = {1965--1974},
  ee            = {http://dx.doi.org/10.1109/TVLSI.2012.2227849},
  doi           = {10.1109/TVLSI.2012.2227849},
  issn          = {1063-8210},
  keywords      = {8-b microcontroller, AES, ECDSA, elliptic curve cryptography, embedded system, implementation security, NFC, RFID, VLSI design},
  url           = {http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6393505},
  abstract      = {This article presents the design and implementation of a complete Near-Field Communication (NFC) tag system that supports high-security features. The tag design contains all hardware modules required for a practical realization, which are: an analog 13.56\,MHz Radio-Frequency Identification (RFID) front-end, a digital part including a tiny (programmable) 8-bit microcontroller, a framing logic for data transmission, a memory unit, and a crypto unit. All components have been highly optimized to meet the fierce requirements of passively powered RFID devices while providing a high level of flexibility and security. The tag is fully compliant to the NFC Forum \mbox{Type-4} specification and supports the ISO/IEC\,14443A (layer 1-4) communication protocol as well as block transmission according to ISO/IEC\,7816. As security features, it supports encryption and decryption using the Advanced Encryption Standard (AES-128), the generation of digital signatures using the Elliptic Curve Digital Signature Algorithm (ECDSA) according to \mbox{NIST P-192}, and it includes several countermeasures against common implementation attacks such as side-channel attacks and fault analyses. The chip has been fabricated in a 0.35\,\textmu m CMOS process technology and requires 49\,999\,GEs of chip area in total (including digital parts and analog front-end). Finally, we present a practical realization of our design that can be powered passively by a conventional NFC-enabled mobile phone for realizing proof-of-origin applications to prevent counterfeiting of goods or to provide location-aware services using RFID technology.}