author        = {Markus Pelnar and Michael M\"uhlberghuber and Michael Hutter},
  title         = {Putting Together What Fits Together - GrAEStl},
  booktitle     = {Smart Card Research and Advanced Applications -- CARDIS 2012, 11th International Conference, Graz, Austria, November 28-30},
  year          = {2012},
  editor        = {Stefan Mangard},
  series        = {Lecture Notes in Computer Science},
  isbn          = {978-3-642-37287-2},
  ee            = {http://dx.doi.org/10.1007/978-3-642-37288-9_12},
  volume        = {7771},
  pages         = {173--187},
  abstract      = {We present GrAEStl, a combined hardware architecture for the Advanced Encryption Standard (AES) and Groestl, one of the final round candidates of the SHA-3 hash competition. GrAEStl has been designed for low-resource devices implementing AES-128 (encryption and decryption) as well as Groestl-256 (tweaked version). We applied several resource-sharing optimizations and based our design on an 8/16-bit datapath. As a feature, we aim for high flexibility by targeting both ASIC and FPGA platforms and do not include technology or platform-dependent components such as RAM macros, DSPs, or Block RAMs. Our ASIC implementation (fabricated in a 0.18um CMOS process) needs only 16.5 kGEs and requires 742/1,025 clock cycles for encryption/decryption and 3,093 clock cycles for hashing one message block. On a Xilinx Spartan-3 FPGA, our design requires 956 logic slices and 302 logic slices on a Xilinx Virtex-6. Both stand-alone implementations of AES and Groestl outperform existing FPGA solutions regarding low-area design by needing 79% and 50% less resources as compared to existing work. GrAEStl is the first combined AES and Groestl implementation that has been fabricated as an ASIC.}